The invention relates to CMOS based image sensors and more particularly to camera on a chip designs that are based on CMOS active pixel sensors.
The are numerous prior art solid state imaging devices. Most common are Charge Coupled Device (CCD) based sensors. CCD sensors within the prior art lack very large scale integration (VLSI) that is employed in modern CMOS devices and in making the cameras that employ these CCD sensors require separate integrated circuits to provide timing, control and clock driver circuitry, therefore, resulting in larger and more expensive to produce cameras.
Additionally within the prior art are a number image sensing devices that have employed CMOS technology to make the solid state imagers. Among these prior art devices are teachings of integrating the analog to digital converter on the same chip as the image sensor. A CMOS image sensor of this type is described in a paper entitled xe2x80x9cAn Addressable 256xc3x97256 Photodiode Sensor Array With An 8-Bit Digital Outputxe2x80x9d in Analog Integrated Circuits and Signal Processing 4, pp. 37-49 (1993) by Janssen et al. Other prior art devices have integrated on chip timing generation such as those described by Nixon et al in a paper entitled xe2x80x9c256xc3x97256 CMOS Active Pixel Sensor Camera-on-a-Chipxe2x80x9d, in 1996 IEEE International Solid-State Circuits Conference Digest of Papers, p. 178-179. However, larger scale integration is lacking within these prior art CMOS devices.
The prior art is also silent towards a coordinated design that allows for external digital interface that can control the image sensing device.
It should be apparent from the foregoing discussion that there remains a need within the art for a CMOS based imager that provides large scale integration sufficient to provide timing, control and clock circuitry and a digital interface that can control the solid state imaging device.
This invention addresses the aforementioned shortcomings within the prior art by providing an architecture of a digital camera-on-chip, built using an active pixel sensor (APS) employing Complementary Metal Oxide Semiconductor (CMOS) technology. The elements of the architectural design comprises functional blocks and their respective interconnections required to operate the APS, which in the preferred embodiment employs a Pinned Photo Diode as its photodetector element. Employing CMOS technology allows integration of timing, control, analog to digital conversion, and incorporation of a digital interface onto a single chip with the photodetecting element array.
The large scale integration taught by the present invention allows features such as electronic zoom and windowing capability. The features provided can be controlled by logic within a digital interface. A free running mode (default operational mode) provides a full resolution image that is independent of the windowing/zoom logic therefore, not requiring control signals from the digital interface. A Photometeric mode allows for selection of groups of pixels to determine the proper parameters such as exposure control. This exposure is effected by proper timing of the electronic shutter. A variety of sleep modes can provide power savings of varying degrees.
The architecture of this CMOS APS comprises of the following connected blocks x-y addressable pixel array timing generation and external interface control logic, programmable Analog to Digital Converter (ADC) and associated signal processing circuitry.
These and other features are provided by a CMOS based image sensor having
An image sensor device comprising:
a silicon substrate having a plurality of CMOS circuit formed thereon;
a pixel array having a plurality of rows and a plurality of columns formed within the substrate;
a timing control logic block formed within the substrate;
a row addressing circuit formed within the substrate and operatively connected to each pixel array and the timing control circuit, the row addressing circuit having a row bus that provides address lines to each row in the pixel array;
a column addressing circuit formed within the substrate;
a pixel timing circuit formed within the substrate;
a signal processing circuit contained within the substrate; and
an interface circuit coupled to external computational means for provision of commands directing the sensor to generate address and control signals to the sensor device, the interface circuit being operatively coupled to the timing control logic, the pixel timing circuit, the row addressing circuit and the column addressing circuit.